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HT68FB30/HT68FB40/HT68FB50/HT68FB60 Enhanced I/O Flash Type 8-Bit MCU with EEPROM & USB Interface
Features
MCU Features
* Operating voltage: * Watchdog Timer function * Up to 39 bidirectional I/O lines * Software controlled 4-SCOM lines LCD driver with
fSYS= 8MHz at 2.2V~5.5V fSYS= 12MHz at 2.7V~5.5V fSYS= 20MHz at 4.5V~5.5V
* Up to 0.2ms instruction cycle with 20MHz system
1/2 bias
* Multiple pin-shared external interrupts * Multiple Timer Module for time measure, input
clock at VDD=5V
* Power down and wake-up functions to reduce
capture, compare match output, PWM output or single pulse output functions
* Serial Interface Module -- SIM for SPI or I C * Dual Comparator functions * Dual Time-Base functions for generation of fixed
2
power consumption
* Five oscillators - External High Speed Xtal - External 32.768kHz Xtal - External RC - Internal High Speed -- no ext. components - Internal 32kHz -- no ext. components * Multi-mode operation: NORMAL, SLOW, IDLE and
time interrupt signal
* Low voltage reset function * Low voltage detect function
SLEEP
* Fully integrated internal 4MHz, 8MHz and 12MHz
SPI to USB chip Features
* Fully compliant with USB 2.0 Full-Speed
oscillator requires no external components
* All instructions executed in one or two instruction
specification
* 6 endpoints (including endpoint 0) * FIFO: 8, 8, 8, 64, 8, 64 for endpoint 0 ~ endpoint 5
cycles
* Table read instructions * 63 powerful instructions * Up to 8 subroutine nesting levels * Bit manipulation instruction
respectively
* Suspend Mode and Remote Wake-up function * Multiple USB interrupt generation sources: endpoint
access, suspend, resume and reset signals
* CMOS clock input with frequency of 6MHz/12MHz
MCU Peripheral Features
* Flash Program Memory: 1K14 ~ 12K16 * RAM Data Memory: 648 ~ 5768 * EEPROM Memory: 328 ~ 2568
for the USB PLL clock
Rev. 1.10
1
June 4, 2010
HT68FB30/HT68FB40/HT68FB50/HT68FB60
General Description
The HT68FBx0 series of devices are Flash Memory I/O type 8-bit high performance RISC architecture microcontrollers with a USB interface. Offering users the convenience of Flash Memory multi-programming features, these devices also include a wide range of functions and features. Other memory includes an area of RAM Data Memory as well as an area of EEPROM memory for storage of non-volatile data such as serial numbers, calibration data etc. Analog feature includes dual comparator functions. Multiple and extremely flexible Timer Modules provide timing, pulse generation and PWM generation functions. Communication with the outside world is catered for by 2 including fully integrated SPI or I C interface functions, two popular interfaces which provide designers with a means of easy communication with external peripheral hardware. Protective features such as an internal Watchdog Timer, Low Voltage Reset and Low Voltage Detector coupled with excellent noise immunity and ESD protection ensure that reliable operation is maintained in hostile electrical environments. A full choice of HXT, LXT, ERC, HIRC and LIRC oscillator functions are provided including a fully integrated system oscillator which requires no external components for its implementation. The ability to operate and switch dynamically between a range of operating modes using different clock sources gives users the ability to optimise microcontroller operation and minimize power consumption. The device contains a single USB Full-speed interface to allow data communication with an external USB host controller. It is particularly suitable for applications which require data communication between PCs and peripheral USB hardware. An extensive choice of oscillator functions is provided including a fully integrated system oscillator which requires no external components for its implementation. The ability to operate and switch dynamically between a range of operating modes using different clock sources gives users the ability to optimise microcontroller operation and minimise power consumption. The devices also include flexible I/O programming features, Time-Base functions and a range of other features.
Selection Guide
Most features are common to all devices, the main feature distinguishing them are Memory capacity, I/O counts, TM features, stack capacity and package types. The following table summarises the main features of each device.
Part No. HT68FB30 VDD 2.2V~ 5.5V 2.2V~ 5.5V 2.2V~ 5.5V 2.2V~ 5.5V Program Memory 2K14 Data Memory 968 Data EEPROM 648 I/O 16 Ext. Int. 2 Timer Module 10-bit CTM1 10-bit ETM1 10-bit CTM1 10-bit ETM1 10-bit STM1 10-bit CTM2 10-bit ETM1 10-bit STM1 10-bit CTM2 10-bit ETM1 10-bit STM1 Interface (SPI/I2C) O O USB O O Stack 4 Package 28SKDIP/SOP/SSOP 44QFP/LQFP 48QFN 44QFP/LQFP 48QFN 44/52QFP 40/48QFN
HT68FB40
4K15
1928
1288
33
2
8
HT68FB50
8K16
3848
2568
34
2
O
O
8
HT68FB60
12K16
5768
2568
39
4
O
O
8
Note:
As devices exist in more than one package format, the table reflects the situation for the package with the most pins.
Rev. 1.10
2
June 4, 2010
HT68FB30/HT68FB40/HT68FB50/HT68FB60
Block Diagram
The following block diagram illustrates the dual-chip structure of the devices, where an individual MCU and SPI to USB chips are combined into a single package.
VDD
VDD I/O TM p o rts p in s H T68Fx0 SCK SDO SDI SCS P IN T PCK VSS SCK SDI SDO SCS IN T C LKI
VDD
V33O H T45B 0K UDP UDN
IN T p in s SCOM OSC p in s p in s RES
VSS
VSS
VSSU
VDD
VDDU
VDD I/O TM p o rts p in s H T68Fx0 SCK SDO SDI SCS P IN T PCK VSS SCK SDI SDO SCS IN T C LKI
VDD
V33O H T45B 0K UDP UDN
IN T p in s SCOM OSC p in s p in s RES
VSS
VSS
VSSU
Internal Chip Interconnection Diagram Note: The ground pins of the internal chips are NOT connected together. On some devices the positive power supply pins are connected together and on some they remain independent.
Rev. 1.10
3
June 4, 2010
HT68FB30/HT68FB40/HT68FB50/HT68FB60
Low V o lta g e D e te c t Low V o lta g e R eset
W a tc h d o g T im e r R eset C ir c u it 8 - b it R IS C MCU C o re In te rru p t C o n tr o lle r E x te rn a l R C /X ta l O s c illa to r s 32768H z O s c illa to r In te rn a l R C O s c illa to r s
F la s h /E E P R O M P r o g r a m m in g C ir c u itr y
S ta c k
F la s h P ro g ra m M e m o ry
EEPROM D a ta M e m o ry
T im e B a s e
RAM D a ta M e m o ry
C o m p a ra to rs
I/O
USB M o d u le
T im e r M o d u le s
Pin Assignment
P A 1 /T P 1 A P A 0 /C 0 X /T P 0 _ 0 VSS P B 4 /X T 2 P B 3 /X T 1 P B 2 /O S C 2 P B 1 /O S C 1 VDD & VDDU P B 0 /R E S NC NC NC NC NC NC NC NC NC NC V33O UDP UDN VSSU P D 6 /[S C K /S C L ] P B 7 /[S D I/S D A ] P B 6 /[S D O ] NC P B 5 /S C S P A 7 /S C K /S C L P A 6 /S D I/S D A P A 5 /C 1 X /S D O P A 4 /IN T 1 /T C K 1 P A 3 /IN T 0 /C 0 P A 2 /T C K 0 /C 0 + P A 1 /T P 1 A P A 0 /C 0 X /T P 0 _ 0 NC P F 1 /[C 1 X ]
1 2 3 4 5 6 7 8 10 11 12 13 1415 16 1718 19 202122 23 24 9 48 47 46 45 4443 4241 403938 37 36 35 34 33 32
1 2 3 4 5 6 7 8 9 10 11 12 13 14
28 27 26 25 24 23 22 21 20 19 18 17 16 15
P A 2 /T C K 0 /C 0 + P A 3 /IN T 0 /C 0 P A 4 /IN T 1 /T C K 1 P A 5 /C 1 X /S D O P A 6 /S D I/S D A P A 7 /S C K /S C L P B 5 /S C S P C 2 /P C K /C 1 + P C 3 /P IN T /C 1 VSSU UDN UDP V33O NC NC NC NC NC NC V33O UDP UDN VSSU P B 7 /[S D I/S D A ] P B 6 /[S D O ]
H T68FB 30 2 8 S K D IP -A /S O P -A /S S O P -A
H T68FB 40 4 8 Q F N -A
31 30 29 28 27 26 25
NC PD PD PE PE PE PE PC PC
0 1 2 3
4 /[T P 2 _ 1 ] 5 /[T P 0 _ 1 ]
NC P C 0 /T P 1 B _ 0 /S C O M 0 P C 1 /T P 1 B _ 1 /S C O M 1
6 /[T P 0 _ 0 ]/S C O M 2 7 /[T P 1 A ]/S C O M 3
P B 5 /S C S P A 7 /S C K /S C L P A 6 /S D I/S D A P A 5 /C 1 X /S D O P A 4 /IN T 1 /T C K 1 P A 3 /IN T 0 /C 0 P A 2 /T C K 0 /C 0 + P A 1 /T P 1 A P A 0 /C 0 X /T P 0 _ 0 P F 1 /[C 1 X ] P F 0 /[C 0 X ]
1 2 3 4 5 6 7 8 10 11 9
44 43 42 41403938 37 363534
33 32 31 30
H T68FB 40 4 4 Q F P -A /L Q F P -A
29 28 27 26 25 24 23
12 131415 1617 1819 20 2122
NC PD PD PE PE PE PE PC PC PC PC 0 1 2 3
4 /[T P 2 _ 1 ] 5 /[T P 0 _ 1 ]
6 /[T 7 /[T 0 /T 1 /T
P0_ P1A P1B P1B
0 ]/S ]/S C _ 0 /S _ 1 /S
CO OM CO CO
M2 3 M0 M1
PE4 PE5 PB0 VDD PB1 PB2 PB3 PB4 VSS PE6 PE7
PE4 PE5 PB0 VDD PB1 PB2 PB3 PB4 VSS PE6 PE7 PF0 /[IN T 0 ] /[IN T 1 ] /[C 0 X ] /R E & /O S /O S /X T /X T S VDDU C1 C2 2 1 /[T P 1 B _ 2 ]
/[IN T 0 ] /[IN T 1 ]
/R E & /O S /O S /X T /X T S VDDU C1 C2 2 1
/[T P 1 B _ 2 ]
Rev. 1.10
4
June 4, 2010
HT68FB30/HT68FB40/HT68FB50/HT68FB60
NC NC NC NC NC V33O UDP UDN VSSU P B 7 /[S D I/S D A ] P B 6 /[S D O ] N N N N N V33 UD UD VSS P D 7 /[S C P D 6 /[S C K /S C P B 7 /[S D I/S D C C C C C O P N U S] L] A] P B 6 /[S D O ] P B 5 /S C S P A 7 /S C K /S C L P A 6 /S D I/S D A P A 5 /C 1 X /S D O P A 4 /IN T 1 /T C K 1 P A 3 /IN T 0 /C 0 P A 2 /T C K 0 /C 0 + P A 1 /T P 1 A P A 0 /C 0 X /T P 0 _ 0 NC P F 1 /[C 1 X ]
1 2 3 4 5 6 7 8 10 11 12 13 1415 16 1718 19 202122 23 24 9 48 47 46 45 4443 4241 403938 37 36 35 34 33 32
H T68FB 50 4 8 Q F N -A
31 30 29 28 27 26 25
NC PD PD PE PE PE PE PC PC
0 1 2
4 /[T P 2 _ 1 ] 5 /[T P 0 _ 1 ]
NC P C 0 /T P 1 B _ 0 /S C O M 0 P C 1 /T P 1 B _ 1 /S C O M 1
3 /[T P 3 _ 1 ] 6 /[T P 0 _ 0 ]/S C O M 2 7 /[T P 1 A ]/S C O M 3
P B 5 /S C S P A 7 /S C K /S C L P A 6 /S D I/S D A P A 5 /C 1 X /S D O P A 4 /IN T 1 /T C K 1 P A 3 /IN T 0 /C 0 P A 2 /T C K 0 /C 0 + P A 1 /T P 1 A P A 0 /C 0 X /T P 0 _ 0 P F 1 /[C 1 X ] P F 0 /[C 0 X ]
1 2 3 4 5 6 7 8 10 11 9
44 43 42 41403938 37 363534
33 32 31 30
H T68FB 50 4 4 Q F P -A /L Q F P -A
29 28 27 26 25 24 23
12 131415 1617 1819 20 2122
NC PD PD PE PE PE PE PC PC PC PC
4 /[T P 5 /[T P 0 /[IN 1 /[IN 2 /[IN 3 /[T P 6 /[T P 7 /[T P 0 /T P 1 /T P
2_1] 0_1] T0] T1] T2] 3_1] 0 _ 0 ]/S 1 A ]/S C 1 B _ 0 /S 1 B _ 1 /S
CO OM CO CO
M2 3 M0 M1
PE4 PE5 PB0 VDD PB1 PB2 PB3 PB4 VSS PE6 PE7
PE4 PE5 PB0 VDD PB1 PB2 PB3 PB4 VSS PE6 PE7 PF0 /[IN T 0 ] /[IN T 1 ] /[C 0 X ] U VDDU P A 7 /S C K /S C L P A 6 /S D I/S D A P A 5 /C 1 X /S D O P A 4 /IN T 1 /T C K 1 P A 3 /IN T 0 /C 0 P A 2 /T C K 0 /C 0 + P A 1 /T P 1 A P A 0 /C 0 X /T P 0 _ 0 P F 1 /[C 1 X ]
1 2 3 4 5 6 7 8 9 10 11 1213 14 1516 1718 19 20 403938 37 363534 33 32 31 1 2 3 4 5 6 7 8 10 11 12 13 1415 16 1718 19 202122 23 24 9 48 47 46 45 4443 4241 403938 37
/[IN T 0 ] /[IN T 1 ]
/[T P 1 B _ 2 ] /[T P 3 _ 0 ] /R E S & VDDU /O S C 1 /O S C 2 /X T 1 /X T 2
/[T P 1 B _ 2 ] /[T P 3 _ 0 ] /R E S & VDDU /O S C 1 /O S C 2 /X T 1 /X T 2 O N H T68FB 60 4 0 Q F N -A P
30 29 28 27 26 25 24 23 22 21
V3 U U VD VS P B 6 /[S D
N N N N N V33 UD UD N VSS C NC PD PD PE PG PC PC PC PC PE 4 /[T P 2 _ 1 ] 5 /[T P 0 _ 1 ] 0 /[IN T 0 ] 1 /[C 1 X ] 6 /[T P 0 _ 0 ]/S 7 /[T P 1 A ]/S C 0 /T P 1 B _ 0 /S 1 /T P 1 B _ 1 /S 4 /[T P 1 B _ 2 ] CO OM CO CO M2 3 M0 M1 P B 5 /S C S P A 7 /S C K /S C L P A 6 /S D I/S D A P A 5 /C 1 X /S D O P A 4 /IN T 1 /T C K 1 P A 3 /IN T 0 /C 0 P A 2 /T C K 0 /C 0 + P A 1 /T P 1 A P A 0 /C 0 X /T P 0 _ 0 P F 1 /[C 1 X ] P F 0 /[C 0 X ]
1 2 3 4 5 6 7 8 9 10 11
NC NC NC NC NC 3O DP DN DU SU O]
C
44 43 42 41403938 37 363534 33 32 31 30
C H T68FB 60 4 4 Q F P -A
29 28 27 26 25 24 12 131415 1617 1819 20 2122 23
C NC PD PD PE PE PE PE PC PC PC PC 4 /[T P 5 /[T P 0 /[IN 1 /[IN 2 /[IN 3 /[T P 6 /[T P 7 /[T P 0 /T P 1 /T P 2_1] 0_1] T0] T1] T2] 3_1] 0 _ 0 ]/S 1 A ]/S C 1 B _ 0 /S 1 B _ 1 /S CO OM CO CO M2 3 M0 M1 PB0 VDD PB1 PB2 PB3 PB4 VSS PE6 PE7 PF0 /[IN T 0 ] /[IN T 1 ] /[C 0 X ] /O S /O S /X T /X T 2 C2 C1
36 35 34 33 32
C PE4 PE5 PB0 VDD PB1 PB2 PB3 PB4 VSS PE6 PE7 /R E S /[IN T 0 ] /[IN T 1 ] /O S /O S /X T /X T /[T P 1 B _ 2 ] /[T P 3 _ 0 ] /R E S 1 2 1 C2 C1 V3 U U VD VS P B 6 /[S D P P NC NC NC NC NC V33O UDP UDN VDDU VSSU P B 7 /[S D I/S D A ] P B 6 /[S D O ] NC P B 5 /S C S P A 7 /S C K /S C L P A 6 /S D I/S D A P A 5 /C 1 X /S D O P A 4 /IN T 1 /T C K 1 P A 3 /IN T 0 /C 0 P A 2 /T C K 0 /C 0 + P A 1 /T P 1 A P A 0 /C 0 X /T P 0 _ 0 NC P F 1 /[C 1 X ] H T68FB 60 4 8 Q F N -A
31 30 29 28 27 26 25
C NC PD PD PE PE PE PE PC PC NC P C 0 /T P 1 B _ 0 /S C O M 0 P C 1 /T P 1 B _ 1 /S C O M 1 4 /[T 5 /[T 0 /[IN 1 /[IN 2 /[IN 3 /[T 6 /[T 7 /[T P2_1] P0_1] T0] T1] T2] P3_1] P 0 _ 0 ]/S C O M 2 P 1 A ]/S C O M 3 PF3 PF2 P B 5 /S C S P A 7 /S C K /S C L P A 6 /S D I/S D A P A 5 /C 1 X /S D O P A 4 /IN T 1 /T C K 1 P A 3 /IN T 0 /C 0 P A 2 /T C K 0 /C 0 + P A 1 /T P 1 A P A 0 /C 0 X /T P 0 _ 0 P F 1 /[C 1 X ] P F 0 /[C 0 X ]
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 52 51 50 49 48 47 46 45 44 43 42 41 40
NC NC NC NC NC 3O DP DN DU SU O] F5
39 38 37 36 35
F4
H T68FB 50 5 2 Q F P -A
34 33 32 31 30 29 28 27
NC PD PD PE PE PE PE PF PF PG PG PC PC 6 7
4 /[T 5 /[T 0 /[IN 1 /[IN 2 /[IN 3 /[T 0 /[C 1 /[C 6 /[T 7 /[T
P2_1] P0_1] T0] T1] T2] P3_1] 0X 1X P0 P1 ] ] _ 0 ]/S C O M 2 A ]/S C O M 3
PC PC PE PE PB VD PB PB PB PB VS PE PE 6 /[IN T 0 ] 7 /[IN T 1 ] S 0 /T 1 /T 4 /[T 5 /[T 0 /R D 1 /O 2 /O 3 /X 4 /X
PE4 PE5 PB0 VDD PB1 PB2 PB3 PB4 VSS PE6 PE7 PF0 /[IN T 0 ] /[IN T 1 ] /[C 0 X ] /O S /O S /X T /X T 2 C2 C1 1 /[T P 1 B _ 2 ] /[T P 3 _ 0 ] /R E S
P1 P1 P1 P3 ES
T2
SC1 SC2 T1
B_ B_ B_ _0 0 /S C O M 0 1 /S C O M 1 2] ]
Note:
1. Bracketed pin names indicate non-default pinout remapping locations. 2. For pin-shared pin functions, pin names to the right side of the / sign have higher priority. 3. VDD & AVDD & VDDU means the VDD, AVDD and VDDU pins are bonded together.
Rev. 1.10
5
June 4, 2010
HT68FB30/HT68FB40/HT68FB50/HT68FB60
Pin Description
With the exception of the power pins, all pins on these devices can be referenced by their Port name, e.g. PA.0, PA.1 etc, which refer to the digital I/O function of the pins. However these Port pins are also shared with other function such as the Analog to Digital Converter, Serial Port pins, etc. The function of each pin is listed in the following tables, however the details behind how each pin is configured is contained in individual MCU and SPI to USB chip datasheet. The important point to note here is that some I/O lines are not bonded to the external pins. Users should take special care of these I/O port lines. Refer to the Hardware Considerations section for more details. HT68FB30 Pin Name PA0~PA7 PB0~PB5 PC2~PC3 C0-, C1C0+, C1+ C0X, C1X Port A Port B Port C Comparator 0, 1 input Comparator 0, 1 input Comparator 0, 1 output 3/4 TMPC0 TMPC0 3/4 PRM0 PRM0 PRM0 PRM0 PRM0 PRM0 PRM0 PRM0 CO CO CO CO CO 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 CP0C CP1C Function OP PAWU PAPU PBPU PCPU I/T ST ST ST AN AN 3/4 ST ST ST ST ST 3/4 ST 3/4 ST ST ST ST HXT 3/4 LXT 3/4 ST PWR PWR ST ST 3/4 PWR PWR 3/4 O/T CMOS CMOS CMOS 3/4 3/4 CMOS 3/4 CMOS CMOS 3/4 3/4 CMOS 3/4 CMOS CMOS CMOS NMOS NMOS 3/4 HXT 3/4 LXT 3/4 3/4 3/4 CMOS CMOS 3/4 3/4 3/4 3/4 Pin-Shared Mapping 3/4 3/4 3/4 PA3, PC3 PA2, PC2 PA0, PA5 PA2, PA4 PA0 PA1 PA3, PA4 PC3 or PC4 PC2 or PC5 PA6 or PC0 PA5 or PC1 PB5 or PC6 PA7 or PC7 PA7 PA6 PB1 PB2 PB3 PB4 PB0 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4
TCK0, TCK1 TM0, TM1 input TP0_0 TP1A INT0, INT1 PINT PCK SDI SDO SCS SCK SCL SDA OSC1 OSC2 XT1 XT2 RES VDD VSS UDP UDN V33O VDDU VSSU NC TM0 I/O TM1 I/O External interrupt 0, 1 Peripheral Interrupt *** Peripheral Clock Output *** SPI data input *** SPI data output *** SPI slave select *** SPI serial clock *** I C clock I C data HXT/ERC pin HXT pin LXT pin LXT pin Reset input MCU power supply * MCU ground USB D+ pin USB D- pin 3.3V regulator output pin USB power supply * USB ground Not connected, can not be used
2 2
Rev. 1.10
6
June 4, 2010
HT68FB30/HT68FB40/HT68FB50/HT68FB60
Note: I/T: Input type; O/T: Output type OP: Optional by configuration option (CO) or register option PWR: Power; CO: Configuration option; ST: Schmitt Trigger input CMOS: CMOS output; NMOS: NMOS output AN: Analog input pin HXT: High frequency crystal oscillator LXT: Low frequency crystal oscillator *: VDD is the device power supply while VDDU is the USB power supply respectively. The VDDU pin is bonded together internally with VDD. **: When the PINT, PCK and SPI functions are pin-shared remapping to PC4~PC5, PC0~PC1 and PC6~PC7 pins, the SPI pins are to be used as the master SPI signal to communicate with the slave SPI in HT45B0K along with the PINT and PCK pins used as the interrupt input and clock output connected to the SPI to USB chip to control the overall USB functions. HT68FB40 Pin Name PA0~PA7 PB0~PB7 PC0~PC1, PC6~PC7 PD4~PD6 PE0~PE7 PF0~PF1 C0C0+ C0X, C1X Port A Port B Port C Port D Port E Port F Comparator 0 input CP0C Comparator 0 input Comparator 0, 1 output CP0C CP1C PRM0 PRM1 TMPC0 PRM2 TMPC0 PRM2 TMPC0 PRM2 TMPC1 PRM2 PRM1 PRM0 PRM0 PRM0 PRM0 PRM0 PRM0 PRM0 AN 3/4 ST ST ST Function OP PAWU PAPU PBPU PCPU PDPU PEPU PFPU I/T ST ST ST ST ST ST AN O/T CMOS CMOS CMOS CMOS CMOS CMOS 3/4 3/4 CMOS 3/4 CMOS CMOS Pin-Shared Mapping 3/4 3/4 3/4 3/4 3/4 3/4 PA3 PA2 PA0, PA5 or PF0, 3/4 PA2, PA4, 3/4 PA0, 3/4, or PC6, PD5 PA1 or PC7 PC0, PC1, 3/4 or 3/4, 3/4, PE4 3/4 or PD4 PA3, PA4 or PE6, PE7 3/4 or PC4 3/4 or PC5 PA6 or PD2 or PB7 PA5 or PD3 or PB6 PB5 or PD0 or PD7 PA7 or PD1 or PD6 PA7 or PD1 or PD6
TCK0, TCK1 TM0, TM1 input TP0_0, TP0_1 TP1A TP1B_0~ TP1B_2 TP2_1 INT0, INT1 PINT PCK SDI SDO SCS SCK SCL TM0 I/O TM1 I/O
TM1 I/O
ST
CMOS
TM2 I/O External interrupt 0, 1 Peripheral Interrupt *** Peripheral Clock Output *** SPI data input *** SPI data output *** SPI slave select *** SPI serial clock *** I C clock
2
ST ST ST 3/4 ST 3/4 ST ST ST
CMOS 3/4 3/4 CMOS 3/4 CMOS CMOS CMOS NMOS
Rev. 1.10
7
June 4, 2010
HT68FB30/HT68FB40/HT68FB50/HT68FB60
Pin Name SDA SCOM0~ SCOM3 OSC1 OSC2 XT1 XT2 RES VDD VSS UDP UDN V33O VDDU VSSU NC Note: I C data SCOM0~SCOM3 HXT/ERC pin HXT pin LXT pin LXT pin Reset input MCU power supply * MCU ground ** USB D+ pin USB D- pin 3.3V regulator output pin USB power supply USB ground Not connected, can not be used I/T: Input type; O/T: Output type OP: Optional by configuration option (CO) or register option PWR: Power; CO: Configuration option; ST: Schmitt Trigger input CMOS: CMOS output; NMOS: NMOS output SCOM: Software controlled LCD COM; AN: Analog input pin HXT: High frequency crystal oscillator LXT: Low frequency crystal oscillator *: VDD is the device power supply while VDDU is the USB power supply respectively. The VDDU pin is bonded together internally with VDD. **: When the PINT, PCK and SPI functions are pin-shared remapping to PC4~PC5 and PD0~PD3 pins, the SPI pins are to be used as the master SPI signal to communicate with the slave SPI in HT45B0K along with the PINT and PCK pins used as the interrupt input and clock output connected to the SPI to USB chip to control the overall USB functions.
2
Function
OP PRM0 SCOMC CO CO CO CO CO 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4
I/T ST 3/4 HXT 3/4 LXT 3/4 ST PWR PWR ST ST 3/4 PWR PWR 3/4
O/T NMOS SCOM 3/4 HXT 3/4 LXT 3/4 3/4 3/4 CMOS CMOS 3/4 3/4 3/4 3/4
Pin-Shared Mapping PA6 or PD2 or PB7 PC0, PC1, PC6, PC7 PB1 PB2 PB3 PB4 PB0 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4
Rev. 1.10
8
June 4, 2010
HT68FB30/HT68FB40/HT68FB50/HT68FB60
HT68FB50 Pin Name PA0~PA7 PB0~PB7 PC0~PC1, PC6~PC7 PD4~PD7 PE0~PE7 PF0~PF1 C0C0+ C0X, C1X Port A Port B Port C Port D Port E Port F Comparator 0 input CP0C Comparator 0 input Comparator 0, 1 output CP0C CP1C PRM0 PRM1 TMPC0 PRM2 TMPC0 PRM2 TMPC0 PRM2 TMPC1 PRM2 TMPC1 PRM2 PRM1 PRM0 PRM0 PRM0 PRM0 PRM0 PRM0 PRM0 PRM0 SCOMC CO CO CO CO CO 3/4 AN 3/4 ST ST ST Function OP PAWU PAPU PBPU PCPU PDPU PEPU PFPU I/T ST ST ST ST ST ST AN O/T CMOS CMOS CMOS CMOS CMOS CMOS 3/4 3/4 CMOS 3/4 CMOS CMOS Pin-Shared Mapping 3/4 3/4 3/4 3/4 3/4 3/4 PA3 PA2 PA0, PA5 or PF0, PF1 PA2, PA4, 3/4, 3/4 PA0, 3/4, or PC6, PD5 PA1 or PC7 PC0, PC1, 3/4 or 3/4, 3/4, PE4 3/4 or PD4 3/4, 3/4, or PE5, PE3 PA3, PA4 or PE6, PE7 3/4 or PC4 3/4 or PC5 PA6 or PD2 or PB7 PA5 or PD3 or PB6 PB5 or PD0 or PD7 PA7 or PD1 or PD6 PA7 or PD1 or PD6 PA6 or PD2 or PB7 PC0, PC1, PC6, PC7 PB1 PB2 PB3 PB4 PB0 3/4
TCK0, TCK1 TM0, TM1 input TP0_0, TP0_1 TP1A TP1B_0~ TP1B_2 TP2_1 TP3_0, TP3_1 INT0, INT1 PINT PCK SDI SDO SCS SCK SCL SDA SCOM0~ SCOM3 OSC1 OSC2 XT1 XT2 RES VDD TM0 I/O TM1 I/O
TM1 I/O
ST
CMOS
TM2 I/O TM3 I/O External interrupt 0, 1 Peripheral Interrupt *** Peripheral Clock Output *** SPI data input *** SPI data output *** SPI slave select *** SPI serial clock *** I C clock I C data SCOM0~SCOM3 HXT/ERC pin HXT pin LXT pin LXT pin Reset input MCU power supply *
2 2
ST ST ST ST 3/4 ST 3/4 ST ST ST ST 3/4 HXT 3/4 LXT 3/4 ST PWR
CMOS CMOS 3/4 3/4 CMOS 3/4 CMOS CMOS CMOS NMOS NMOS SCOM 3/4 HXT 3/4 LXT 3/4 3/4
Rev. 1.10
9
June 4, 2010
HT68FB30/HT68FB40/HT68FB50/HT68FB60
Pin Name VSS UDP UDN V33O VDDU VSSU NC Note: MCU ground ** USB D+ pin USB D- pin 3.3V regulator output pin USB power supply USB ground Not connected, can not be used I/T: Input type; O/T: Output type OP: Optional by configuration option (CO) or register option PWR: Power; CO: Configuration option; ST: Schmitt Trigger input CMOS: CMOS output; NMOS: NMOS output SCOM: Software controlled LCD COM; AN: Analog input pin HXT: High frequency crystal oscillator LXT: Low frequency crystal oscillator *: VDD is the device power supply while VDDU is the USB power supply respectively. The VDDU pin is bonded together internally with VDD. **: When the PINT, PCK and SPI functions are pin-shared remapping to PC4~PC5 and PD0~PD3 pins, the SPI pins are to be used as the master SPI signal to communicate with the slave SPI in HT45B0K along with the PINT and PCK pins used as the interrupt input and clock output connected to the SPI to USB chip to control the overall USB functions. HT68FB60 Pin Name PA0~PA7 PB0~PB6 PC0~PC1, PC6~PC7 PD4~PD5 PE0~PE7 PF0~PF7 PG0~PG1 C0C0+ C0X, C1X Port A Port B Port C Port D Port E Port F Port G Comparator 0 input CP0C Comparator 0 input Comparator 0, 1 output CP0C CP1C PRM0 PRM1 TMPC0 PRM2 TMPC0 PRM2 TMPC0 PRM2 AN 3/4 ST ST ST ST Function OP PAWU PAPU PBPU PCPU PDPU PEPU PFPU PFPU I/T ST ST ST ST ST ST ST AN O/T CMOS CMOS CMOS CMOS CMOS CMOS CMOS 3/4 3/4 CMOS 3/4 CMOS CMOS CMOS Pin-Shared Mapping 3/4 3/4 3/4 3/4 3/4 3/4 3/4 PA3 PA2 PA0, PA5 or PF0, PF1 or PG0, PG1 PA2, PA4, 3/4, 3/4 PA0, 3/4, or PC6, PD5 PA1 or PC7 PC0, PC1, 3/4 or 3/4, 3/4, PE4 Function OP 3/4 3/4 3/4 3/4 3/4 3/4 3/4 I/T PWR ST ST 3/4 PWR PWR 3/4 O/T 3/4 CMOS CMOS 3/4 3/4 3/4 3/4 Pin-Shared Mapping 3/4 3/4 3/4 3/4 3/4 3/4 3/4
TCK0, TCK1 TM0, TM1 input TP0_0, TP0_1 TP1A TP1B_0~ TP1B_2 TM0 I/O TM1 I/O TM1 I/O
Rev. 1.10
10
June 4, 2010
HT68FB30/HT68FB40/HT68FB50/HT68FB60
Pin Name TP2_1 TP3_0, TP3_1 TM2 I/O TM3 I/O Function OP TMPC1 PRM2 TMPC1 PRM2 I/T ST ST O/T CMOS CMOS Pin-Shared Mapping 3/4 or PD4 3/4, 3/4, or PE5, PE3 PA3, PA4, 3/4 or 3/4, 3/4, PE2, PE0, PE1, 3/4, or PE6, PE7, 3/4 3/4 or PC4 3/4 or PC5 PA6 or PD2 PA5 or PB6 or PD1 PB5 or PD0 PA7 or PD3 PA7 PA6 PC0, PC1, PC6, PC7 PB1 PB2 PB3 PB4 PB0 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4
INT0~INT2
External interrupt 0~2
PRM1
ST
3/4
PINT PCK SDI SDO SCS SCK SCL SDA SCOM0~ SCOM3 OSC1 OSC2 XT1 XT2 RES VDD VSS UDP UDN V33O VDDU VSSU NC Note:
Peripheral Interrupt * Peripheral Clock Output * SPI data input * SPI data output * SPI slave select * SPI serial clock * I C clock I C data SCOM0~SCOM3 HXT/ERC pin HXT pin LXT pin LXT pin Reset input MCU power supply MCU ground USB D+ pin USB D- pin 3.3V regulator output pin USB power supply USB ground Not connected, can not be used I/T: Input type; O/T: Output type
2 2
PRM0 PRM0 PRM0 PRM0 PRM0 PRM0 PRM0 PRM0 SCOMC CO CO CO CO CO 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4
ST 3/4 ST 3/4 ST ST ST ST 3/4 HXT 3/4 LXT 3/4 ST PWR PWR ST ST 3/4 PWR PWR 3/4
3/4 CMOS 3/4 CMOS CMOS CMOS NMOS NMOS SCOM 3/4 HXT 3/4 LXT 3/4 3/4 3/4 CMOS CMOS 3/4 3/4 3/4 3/4
OP: Optional by configuration option (CO) or register option PWR: Power; CO: Configuration option; ST: Schmitt Trigger input CMOS: CMOS output; NMOS: NMOS output SCOM: Software controlled LCD COM; AN: Analog input pin HXT: High frequency crystal oscillator LXT: Low frequency crystal oscillator *: When the PINT, PCK and SPI functions are pin-shared remapping to PC4~PC5 and PD0~PD3 pins, the SPI pins are to be used as the master SPI signal to communicate with the slave SPI in HT45B0K along with the PINT and PCK pins used as the interrupt input and clock output connected to the SPI to USB chip to control the overall USB functions.
Rev. 1.10
11
June 4, 2010
HT68FB30/HT68FB40/HT68FB50/HT68FB60
Internally Connected Pins Among the pins mentioned in the tables above several pins are not connected to external package pins. These pins are interconnection pins between the MCU and the SPI to USB chips and are listed in the following table. The description is provided from the SPI to USB chip standpoint. SPI to USB Chip Pin Name SDI SDO SCK Type I O I Description Slave SPI Serial Data In Input Signal Internally connected to the MCU Master SPI SDO output signal Slave SPI Serial Data Out Output Signal Internally connected to the MCU Master SPI SDI input signal Slave SPI Serial Clock Input Signal Internally connected to the MCU Master SPI SCK output signal Slave SPI Device Select Input Signal Internally connected to the MCU Master SPI SCS output signal - connected to pull high resistor Clock Input Signal Internally connected to the MCU Master PCK output signal USB Interrupt Output Signal Internally connected to the MCU Master PINT input signal A USB related interrupt will generate a low pulse signal on this line
SCS
I
CLKI
I
INT
O
Rev. 1.10
12
June 4, 2010
HT68FB30/HT68FB40/HT68FB50/HT68FB60
Functional Description
As these devices packages contain multiple internal chips, for a detailed functional description, users must refer to the relevant individual datasheets for both the MCU and the SPI to USB chips. The following table shows which individual devices are inside each package. Device HT68FB30 HT68FB40 HT68FB50 HT68FB60 MCU HT68F30 HT68F40 HT68F50 HT68F60 SPI to USB Chip HT45B0K HT45B0K HT45B0K HT45B0K
* Power Down and Wake up
The MCU and SPI to USB chip are powered down independently of each other. The method of powering down the MCU is covered in the relevant MCU datasheet. The SPI to USB chip must be powered down before the MCU is powered down. After the device is powered down, it could be also woken up by the SPI to USB chip interrupt except by wake-up sources mentioned in the MCU datasheet. When a USB interrupt occurs on the INT line, it will wake up the MCU if the MCU has entered a power down mode. After the MCU is woken up, the application program must set the corresponding control bits to make the device function normally.
* Interrupts
Multi-chip Internal Devices Although most of the functional description material will be located in the individual datasheets, there are some special considerations which need to be taken into account when using multi-chip devices. These points will be mentioned in the hardware and software consideration sections As the complexity of USB data protocol does not permit comprehensive USB operation information to be provided in the related datasheets, the reader should therefore consult other external information for a detailed USB understanding. Multi-chip Hardware Considerations As these single-package multi-chip devices are composed of an individual MCU and SPI to USB chip, using them together requires the user to take care of some special points.
* Absolute Maximum Ratings
When a USB interrupt occurs, a low pulse will be generated on the INT line and sent to the peripheral interrupt line PINT in the MCU to get the attention of the microcontroller. When the USB interrupt caused by one of the USB interrupt generation sources occurs, if the corresponding interrupt control in the host MCU is enabled and the stack is not full, the program will jump to the corresponding interrupt vector where it can be serviced before returning to the main program. For a USB interrupt to be serviced, in addition to the bits for the corresponding interrupt enable control in the SPI to USB chip being set, the global interrupt enable control and the related interrupt enable control bits in the host MCU must also be set. If these bits are not set, then the interrupt signal will only be a wake-up source and no interrupt will be serviced.
* Unbonded MCU pins
The Absolute Maximum Ratings for the two individual chips must be checked for discrepancies and the necessary care taken in device handling and usage.
* Power Supply
Examination of the block diagram will reveal that the SPI to USB chip Ground pin, VSSU, has no internal connection to the MCU Ground pin, VSS. For this reason these two pins must be connected externally. With the exception of the HT68FB60 device, the SPI to USB chip power supply pin, VDDU, is internally connected to the MCU power supply pin, VDD. For the HT68FB60 device, the SPI to USB chip power supply pin and the MCU power supply pin should be connected together externally. To calculate the power consumption for the devices, the total operating current is the sum of the operating current for the MCU specified in the MCU datasheet and the operating current for the SPI to USB chip listed in its datasheet. Similarly, the standby current is the sum of the two individual chip standby currents.
Examination of the relevant MCU datasheet will reveal that not all of the MCU I/O port lines are bonded out to external pins. As a result special attention regarding initialisation procedures should be paid to these port lines. If the pins are pin-shared with the analog input pins, they will be setup as analog inputs and the corresponding analog circuits will be disabled after a reset. When these pins are set as analog input pins and the relevant analog circuits are disabled, they will not consume any power even if the input pin conditions are not kept as either high or low logic levels. However, if the pins are not pin-shared with analog input pins, they will be setup as input states without pull high resistors after a reset. Users should therefore ensure that these pins are setup in input states with pull high resistors or in output states with either a high or low levels to avoid additional power consumption resulting from floating input pins.
Rev. 1.10
13
June 4, 2010
HT68FB30/HT68FB40/HT68FB50/HT68FB60
Multi-chip Programming Considerations To use the USB function, several important steps must be implemented to ensure that the SPI to USB chip operates normally:
* The SPI pin-remapping function must be properly * The PCK control bit is set to 1 to enable the PCK out-
put as the clock source for the USB external clock input with various PCK output frequencies determined by the PCKP1 and PCKP0 bits in the SIMC0 Register.
PCK output frequency selection bits PCKP1~ PCKP0 in the SIMC0 Register Bit Name Setting Value 1 PCKP1 0 PCKP0
configured when the SPI functional pins of the microcontroller are used to control the SPI to USB chip and for transmission and reception. To ensure proper setup between the MCU Master SPI interface to the SPI to USB chip Slave SPI, the SIM pin-remapping settings for PCK and PINT in the MCU PRM0 register should be setup as shown in the following table.
11, 10, 01 or 00
HT68FB30 PRM0 Register PCK and PINT pin-remap setup Bit Name Setting Value 1 SIMPS0 1 0 PCKPS 1
00: PCK output frequency is fSYS 01: PCK output frequency is fSYS/4 10: PCK output frequency is fSYS/8 11: PCK output frequency is TM0 CCRP match frequency/2 PCK output enable control bit PCKEN in the SIMC0 Register Bit Name Setting Value 4 PCKEN 1
HT68FB40/HT68FB50 PRM0 Register PCK and PINT pin-remap setup Bit Name Setting Value 2 SIMPS1 0 1 SIMPS0 1 0 PCKPS 1
0: Disable PCK output 1: Enable PCK output After the above setup conditions have been implemented, the MCU can enable the SIM interface by setting the SIMEN bit high. The MCU can then begin communication with external USB connected appliances using its SPI interface. The detailed functional descriptions of the MCU Master SPI are provided within the Serial Interface Module section of the relevant MCU datasheet.
HT68FB60 PRM0 Register PCK and PINT pin-remap setup Bit Name Setting Value 2 SIMPS1 1 1 SIMPS0 1 0 PCKPS 1
* The SIM operating mode control bits SIM2~SIM0 in
the SIMC0 register have to be configured to enable the SIM to operate in the SPI master mode with a different SPI clock frequency.
SIM operating mode control bits SIM2~SIM0 in the SIMC0 Register Bit Name Setting Value 2 SIMPS1 1 1 SIMPS0 1 0 PCKPS 1
000: SPI master mode; SPI clock is fSYS/4 001: SPI master mode; SPI clock is fSYS/16 010: SPI master mode; SPI clock is fSYS/64 011: SPI master mode; SPI clock is fTBC 100: SPI master mode; SPI clock is TM0 CCRP match frequency/2 101~111: must not be used
Rev. 1.10
14
June 4, 2010
HT68FB30/HT68FB40/HT68FB50/HT68FB60
Application Circuits
V 0 .0 1 m F * *
DD
VDD Reset C ir c u it RES I/O P o TM P IN T P SCOM P rts in s in s in s
0 .1 m F
1N4148*
10kW ~ 100kW 300W *
0 .1 ~ 1 m F
VSS
OSC C ir c u it S e e O s c illa to r s e c tio n in M C U d a ta s h e e t
OSC1 OSC2 VD V3 U U VS DU 3O DP DN SU
USB A p p lic a tio n C ir c u it S e e A p p lic a tio n C ir c u it in U S B m o d u le d a ta s h e e t
OSC C ir c u it S e e O s c illa to r s e c tio n in M C U d a ta s h e e t
XT1 XT2
Note:
* Recommended component for added ESD protection. ** Recommended component in environments where power line noise is significant.
Rev. 1.10
15
June 4, 2010
HT68FB30/HT68FB40/HT68FB50/HT68FB60
Package Information
28-pin SKDIP (300mil) Outline Dimensions
A
28 15 14 1
B
H C D E F G I
Symbol A B C D E F G H I
Dimensions in inch Min. 1.375 0.278 0.125 0.125 0.016 0.050 3/4 0.295 3/4 Nom. 3/4 3/4 3/4 3/4 3/4 3/4 0.100 3/4 0.375 Dimensions in mm Min. 34.93 7.06 3.18 3.18 0.41 1.27 3/4 7.49 3/4 Nom. 3/4 3/4 3/4 3/4 3/4 3/4 2.54 3/4 9.53 Max. 35.43 7.57 3.43 3.68 0.51 1.78 3/4 8.00 3/4 Max. 1.395 0.298 0.135 0.145 0.020 0.070 3/4 0.315 3/4
Symbol A B C D E F G H I
Rev. 1.10
16
June 4, 2010
HT68FB30/HT68FB40/HT68FB50/HT68FB60
28-pin SOP (300mil) Outline Dimensions
28 A
15 B
1
14
C C' G H D E F
a
* MS-013
Symbol A B C C D E F G H a Symbol A B C C D E F G H a
Dimensions in inch Min. 0.393 0.256 0.012 0.697 3/4 3/4 0.004 0.016 0.008 0 Nom. 3/4 3/4 3/4 3/4 3/4 0.050 3/4 3/4 3/4 3/4 Dimensions in mm Min. 9.98 6.50 0.30 17.70 3/4 3/4 0.10 0.41 0.20 0 Nom. 3/4 3/4 3/4 3/4 3/4 1.27 3/4 3/4 3/4 3/4 Max. 10.64 7.62 0.51 18.11 2.64 3/4 0.30 1.27 0.33 8 Max. 0.419 0.300 0.020 0.713 0.104 3/4 0.012 0.050 0.013 8
Rev. 1.10
17
June 4, 2010
HT68FB30/HT68FB40/HT68FB50/HT68FB60
28-pin SSOP (150mil) Outline Dimensions
28 A
15 B
1 C C'
14
G H a F
D E
Symbol A B C C D E F G H a Symbol A B C C D E F G H a
Dimensions in inch Min. 0.228 0.150 0.008 0.386 0.054 3/4 0.004 0.022 0.007 0 Nom. 3/4 3/4 3/4 3/4 3/4 0.025 3/4 3/4 3/4 3/4 Dimensions in mm Min. 5.79 3.81 0.20 9.80 1.37 3/4 0.10 0.56 0.18 0 Nom. 3/4 3/4 3/4 3/4 3/4 0.64 3/4 3/4 3/4 3/4 Max. 6.20 3.99 0.30 10.01 1.52 3/4 0.25 0.71 0.25 8 Max. 0.244 0.157 0.012 0.394 0.060 3/4 0.010 0.028 0.010 8
Rev. 1.10
18
June 4, 2010
HT68FB30/HT68FB40/HT68FB50/HT68FB60
SAW Type 40-pin (6mm6mm for 0.75mm) QFN Outline Dimensions
D 31 b 30
D2 40 1
E e 21 A1 A3 A L K 20 11 10
E2
* GTK
Symbol A A1 A3 b D E e D2 E2 L K
Dimensions in inch Min. 0.028 0.000 3/4 0.007 3/4 3/4 3/4 0.173 0.173 0.014 0.008 Nom. 0.030 0.001 0.008 0.010 0.236 0.236 0.020 0.177 0.177 0.016 3/4 Dimensions in mm Min. 0.70 0.00 3/4 0.18 3/4 3/4 3/4 4.40 4.40 0.35 0.20 Nom. 0.75 0.02 0.20 0.25 6.00 6.00 0.50 4.50 4.50 0.40 3/4 Max. 0.80 0.05 3/4 0.30 3/4 3/4 3/4 4.55 4.55 0.45 3/4 Max. 0.031 0.002 3/4 0.012 3/4 3/4 3/4 0.179 0.179 0.018 3/4
Symbol A A1 A3 b D E e D2 E2 L K
Rev. 1.10
19
June 4, 2010
HT68FB30/HT68FB40/HT68FB50/HT68FB60
SAW Type 48-pin (7mm7mm) QFN Outline Dimensions
D 37 b 36
D2 48 1
E e 25 A1 A3 A L K 24 13 12
E2
Symbol A A1 A3 b D E e D2 E2 L K
Dimensions in inch Min. 0.028 0.000 3/4 0.007 3/4 3/4 3/4 0.177 0.177 0.012 0.008 Nom. 3/4 3/4 0.008 3/4 0.276 0.276 0.020 3/4 3/4 3/4 3/4 Dimensions in mm Min. 0.70 0.00 3/4 0.18 3/4 3/4 3/4 4.50 4.50 0.30 0.20 Nom. 3/4 3/4 0.203 3/4 7.00 7.00 0.50 3/4 3/4 3/4 3/4 Max. 0.80 0.05 3/4 0.30 3/4 3/4 3/4 5.76 5.76 0.50 3/4 Max. 0.031 0.002 3/4 0.012 3/4 3/4 3/4 0.227 0.227 0.020 3/4
Symbol A A1 A3 b D E e D2 E2 L K
Rev. 1.10
20
June 4, 2010
HT68FB30/HT68FB40/HT68FB50/HT68FB60
44-pin QFP (10mm10mm) Outline Dimensions
C D G 23 I 34 22 L F A B E 44 12 K 1 11 a J 33 H
Symbol A B C D E F G H I J K L a Symbol A B C D E F G H I J K L a
Dimensions in inch Min. 0.512 0.390 0.512 0.390 3/4 3/4 0.075 3/4 0.010 0.029 0.004 3/4 0 Nom. 3/4 3/4 3/4 3/4 0.031 0.012 3/4 3/4 3/4 3/4 3/4 0.004 3/4 Dimensions in mm Min. 13.00 9.90 13.00 9.90 3/4 3/4 1.90 3/4 0.25 0.73 0.10 3/4 0 Nom. 3/4 3/4 3/4 3/4 0.80 0.30 3/4 3/4 3/4 3/4 3/4 0.10 3/4 Max. 13.40 10.10 13.40 10.10 3/4 3/4 2.20 2.70 0.50 0.93 0.20 3/4 7 Max. 0.528 0.398 0.528 0.398 3/4 3/4 0.087 0.106 0.020 0.037 0.008 3/4 7
Rev. 1.10
21
June 4, 2010
HT68FB30/HT68FB40/HT68FB50/HT68FB60
52-pin QFP (14mm14mm) Outline Dimensions
C D 39 27 G H
I 40 26 F A B E
52
14 K J 1 13
Symbol A B C D E F G H I J K L a Symbol A B C D E F G H I J K a
Dimensions in inch Min. 0.681 0.547 0.681 0.547 3/4 3/4 0.098 3/4 3/4 0.029 0.004 3/4 0 Nom. 3/4 3/4 3/4 3/4 0.039 0.016 3/4 3/4 0.004 3/4 3/4 0.004 3/4 Dimensions in mm Min. 17.30 13.90 17.30 13.90 3/4 3/4 2.50 3/4 3/4 0.73 0.10 0 Nom. 3/4 3/4 3/4 3/4 1.00 0.40 3/4 3/4 0.10 3/4 3/4 3/4 Max. 17.50 14.10 17.50 14.10 3/4 3/4 3.10 3.40 3/4 1.03 0.20 7 Max. 0.689 0.555 0.689 0.555 3/4 3/4 0.122 0.134 3/4 0.041 0.008 3/4 7
Rev. 1.10
22
June 4, 2010
HT68FB30/HT68FB40/HT68FB50/HT68FB60
44-pin LQFP (10mm10mm) (FP3.2mm) Outline Dimensions
C D G 23 I 34 22 F A B E 44 12 K 1 11 a J 33 H
Symbol A B C D E F G H I J K a Symbol A B C D E F G H I J K a
Dimensions in inch Min. 0.512 0.390 0.512 0.390 3/4 3/4 0.053 3/4 0.004 0.041 0.004 0 Nom. 0.520 0.394 0.520 0.394 0.031 0.012 0.055 3/4 3/4 0.047 3/4 3/4 Dimensions in mm Min. 13.00 9.90 13.00 9.90 3/4 3/4 1.35 3/4 0.10 1.05 0.10 0 Nom. 13.20 10.00 13.20 10.00 0.80 0.30 1.40 3/4 3/4 1.20 3/4 3/4 Max. 13.40 10.10 13.40 10.10 3/4 3/4 1.45 1.60 0.25 1.35 0.25 7 Max. 0.528 0.398 0.528 0.398 3/4 3/4 0.057 0.063 0.010 0.053 0.008 7
Rev. 1.10
23
June 4, 2010
HT68FB30/HT68FB40/HT68FB50/HT68FB60
Product Tape and Reel Specifications
Reel Dimensions
T2 D
A
B
C
T1
SOP 28W (300mil) Symbol A B C D T1 T2 Description Reel Outer Diameter Reel Inner Diameter Spindle Hole Diameter Key Slit Width Space Between Flange Reel Thickness Dimensions in mm 330.01.0 100.01.5 13.0
+0.5/-0.2
2.00.5 24.8
+0.3/-0.2
30.20.2
SSOP 28S (150mil) Symbol A B C D T1 T2 Description Reel Outer Diameter Reel Inner Diameter Spindle Hole Diameter Key Slit Width Space Between Flange Reel Thickness Dimensions in mm 330.01.0 100.01.5 13.0 16.8
+0.5/-0.2
2.00.5
+0.3/-0.2
22.20.2
Rev. 1.10
24
June 4, 2010
HT68FB30/HT68FB40/HT68FB50/HT68FB60
Carrier Tape Dimensions
D
E F W C
P0
P1
t
B0
D1
P A0
K0
R e e l H o le IC p a c k a g e p in 1 a n d th e r e e l h o le s a r e lo c a te d o n th e s a m e s id e .
SOP 28W (300mil) Symbol W P E F D D1 P0 P1 A0 B0 K0 t C Description Carrier Tape Width Cavity Pitch Perforation Position Cavity to Perforation (Width Direction) Perforation Diameter Cavity Hole Diameter Perforation Pitch Cavity to Perforation (Length Direction) Cavity Length Cavity Width Cavity Depth Carrier Tape Thickness Cover Tape Width Dimensions in mm 24.00.3 12.00.1 1.750.10 11.50.1 1.5 1.50
+0.1/-0.0 +0.25/-0.00
4.00.1 2.00.1 10.850.10 18.340.10 2.970.10 0.350.01 21.30.1
SSOP 28S (150mil) Symbol W P E F D D1 P0 P1 A0 B0 K0 t C Cavity Pitch Perforation Position Cavity to Perforation (Width Direction) Perforation Diameter Cavity Hole Diameter Perforation Pitch Cavity to Perforation (Length Direction) Cavity Length Cavity Width Cavity Depth Carrier Tape Thickness Cover Tape Width Description Carrier Tape Width Dimensions in mm 16.00.3 8.00.1 1.750.1 7.50.1 1.55 1.50
+0.10/-0.00 +0.25/-0.00
4.00.1 2.00.1 6.50.1 10.30.1 2.10.1 0.300.05 13.30.1
Rev. 1.10
25
June 4, 2010
HT68FB30/HT68FB40/HT68FB50/HT68FB60
Holtek Semiconductor Inc. (Headquarters) No.3, Creation Rd. II, Science Park, Hsinchu, Taiwan Tel: 886-3-563-1999 Fax: 886-3-563-1189 http://www.holtek.com.tw Holtek Semiconductor Inc. (Taipei Sales Office) 4F-2, No. 3-2, YuanQu St., Nankang Software Park, Taipei 115, Taiwan Tel: 886-2-2655-7070 Fax: 886-2-2655-7373 Fax: 886-2-2655-7383 (International sales hotline) Holtek Semiconductor Inc. (Shenzhen Sales Office) 5F, Unit A, Productivity Building, No.5 Gaoxin M 2nd Road, Nanshan District, Shenzhen, China 518057 Tel: 86-755-8616-9908, 86-755-8616-9308 Fax: 86-755-8616-9722 Holtek Semiconductor (USA), Inc. (North America Sales Office) 46729 Fremont Blvd., Fremont, CA 94538, USA Tel: 1-510-252-9880 Fax: 1-510-252-9885 http://www.holtek.com
Copyright O 2010 by HOLTEK SEMICONDUCTOR INC. The information appearing in this Data Sheet is believed to be accurate at the time of publication. However, Holtek assumes no responsibility arising from the use of the specifications described. The applications mentioned herein are used solely for the purpose of illustration and Holtek makes no warranty or representation that such applications will be suitable without further modification, nor recommends the use of its products for application that may present a risk to human life due to malfunction or otherwise. Holteks products are not authorized for use as critical components in life support devices or systems. Holtek reserves the right to alter its products without prior notification. For the most up-to-date information, please visit our web site at http://www.holtek.com.tw.
Rev. 1.10
26
June 4, 2010

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